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1 memory all data sheets are subject to change without notice (858) 503-3300 - fax: (858) 503-3301 - www.maxwell.com 4 megabit (512k x 8-bit) 33c408 ?2001 maxwell technologies all rights reserved. cmos sram 12.13.01 rev7 12.20.01 rev 7 1000561 f eatures : ?r ad -p ak ? technology radiation-hardened against natural space radiation ? 524,288 x 8 bit organization total dose hardness: - > 100 krad (si), depending upon space mission ? excellent single event effect - sel th : > 68 mev/mg/cm 2 - seu th : = 3 mev/mg/cm 2 - seu saturated cross section: 6e-9 cm 2 /bit ? package: - 32-pin r ad -p ak ? flat pack - 32-pin non-r ad -p ak ? flat pack ? fast access time: - 20, 25, 30 ns maximum times available ? single 5v + 10% power supply ? fully static operation - no clock or refresh required ? three state outputs ? ttl compatible inputs and outputs ? low power: - standby: 60 ma (ttl); 10 ma (cmos) - operation: 180 ma (20 ns); 170 ma (25 ns); 160 ma (30 ns) d escription : maxwell technologies? 33c408 high-density 4 megabit sram microcircuit features a greater than 100 krad (si) total dose tolerance, depending upon space mission. using maxwell?s radiation-hardened r ad -p ak ? packaging technology, the 33c408 realizes a high density, high performance, and low power consumption. its fully static design eliminates the need for external clocks, while t he cmos circuitry reduces power consumption and provides higher reliability. the 33c408 is equipped with eight common input/output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. the 33c408 features the same advanced 512k x 8-bit sram, high-speed, and low-power demand as the commercial counterpart. maxwell technologies' patented r ad -p ak packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding fo r a lifetime in orbit or space mission. in a geo orbit, r ad -p ak provides greater than 100 krad (si) radiation dose toleranc e. this product is available with screening up to class s. logic diagram
memory 2 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 t able 1. p inout d escription p in s ymbol d escription 12-5, 27, 26, 23, 25, 4, 28, 3, 31, 2, 30, 1 a0-a18 address inputs 29 we write enable 22 cs chip select 24 oe output enable 13-15, 17-21 i/o 1-i/o 8 data inputs/outputs 32 v cc power (+5.0v) 16 v ss ground t able 2. 33c408 a bsolute m aximum r atings p arameter s ymbol m in m ax u nit voltage on v cc supply relative to v ss v cc -0.5 7.0 v voltage on any pin relative to v ss v in , v out -0.5 v cc +0.5 v power dissipation p d -- 1.0 w storage temperature t s -65 +150 c operating temperature t a -55 +125 c t able 3. d elta l imits p arameter v ariation i cc1 10% of stated vaule in table 6 i cc2 10% of stated vaule in table 6 i cc3 10% of stated vaule in table 6 i li 10% of stated vaule in table 6
memory 3 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 t able 4. 33c408 r ecommended o perating c onditions (v cc = 5.0 + 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter s ymbol m in m ax u nit supply voltage v cc 4.5 5.5 v ground v ss 00v input high voltage 1 1. v ih (max) = v cc +2.0v ac (pulse width < 10 ns) for i < 20 ma v ih 2.2 v cc +0.5 v input low voltage 2 2. v il (min) = -2.0v ac(pulse width < 10 ns) for i < 20 ma v il -0.5 0.8 v thermal impedance jc -- 1.21 c/w t able 5. 33c408 c apacitance (f = 1.0 mh z , dv = 3.0v, t a = 25 c) p arameter s ymbol t est c onditions m ax u nits input capacitance 1 cs1 - cs4 , oe , we i/o0-7, i/o8-15, i/o16-23, i/o24-31 1. guaranteed by design. c in v in = 0 v 7 28 7 pf input / output capacitance 1 c out v i/o = 0 v 8 pf t able 6. 33c408 dc e lectrical c haracteristics (v cc = 5v + 10%, t a = -55 to +125 c, unless otherwise specified ) p arameter s ymbol c ondition m in m ax u nit input leakage current i li v in = v ss to v cc -2 2 a output leakage current i lo cs =v ih or oe =v ih or we =v il , v out =v ss to v cc -2 2 a output low voltage v ol i ol = 8ma -- 0.4 v output high voltage v oh i oh = -4ma 2.4 -- v operating current -20 -25 -30 i cc min cycle, 100% duty, cs =v il , i out =0ma, v in = v ih or v il -- -- -- 180 170 160 ma standby power supply cur- rent i sb cs = v ih , min cycle -- 60 ma input capacitance 1 c in v in = 0v, f = 1mhz, t a = 25 c -- 7 pf
memory 4 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 output capacitance 1 c i/o v i/o = 0v -- 8 pf 1. guaranteed by design. t able 7. 33c408 ac o perating c onditions and c haracteristics (v cc = 5.0 + 10%, t a = -55 to +125 c, unless otherwise noted ) p arameter m in t yp m ax u nits input pulse level 0.0 -- 3.0 v output timing measurement reference level -- -- 1.5 v input rise/fall time -- -- 3.0 ns input timing measurement reference level -- -- 1.5 v t able 8. 33c408 ac c haracteristics for r ead c ycle (v cc = 5v + 10%, t a = -55 to +125 c, unless otherwise specified ) p arameter s ymbol m in t yp m ax u nit read cycle time -20 -25 -30 t rc 20 25 30 -- -- -- -- -- -- ns address access time -20 -25 -30 t aa -- -- -- -- -- -- 20 25 30 ns chip select access time -20 -25 -30 t co -- -- -- -- -- -- 20 25 30 ns output enable to output valid -20 -25 -30 t oe -- -- -- -- -- -- 10 12 14 ns chip enable to output in low-z -20 -25 -30 t lz -- -- -- 3 3 3 -- -- -- ns output enable to output in low-z -20 -25 -30 t olz -- -- -- 0 0 0 -- -- -- ns t able 6. 33c408 dc e lectrical c haracteristics (v cc = 5v + 10%, t a = -55 to +125 c, unless otherwise specified ) p arameter s ymbol c ondition m in m ax u nit
memory 5 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 chip deselect to output in high-z -20 -25 -30 t hz -- -- -- 5 6 8 -- -- -- ns output disable to output in high-z -20 -25 -30 t ohz -- -- -- 5 6 8 -- -- -- ns output hold from address change -20 -25 -30 t oh 3 5 6 -- -- -- -- -- -- ns chip select to power up time -20 -25 -30 t pu -- -- -- 0 0 0 -- -- -- ns chip select to power down time -20 -25 -30 t pd -- -- -- 10 15 20 -- -- -- ns t able 9. 33c408 f unctional d escription cs we oe m ode i/o p in s upply c urrent hx 1 1. x = don?t care. x 1 not select high-z i sb , i sb1 l h h output disable high-z i cc l h l read d out i cc llx 1 write d in i cc t able 10. 33c408 ac c haracteristics for w rite c ycle (v cc = 5v + 10%, t a = -55 to +125 c, unless otherwise specified ) p arameter s ymbol m in t yp m ax u nit write cycle time -20 -25 -30 t wc 20 25 30 -- -- -- -- -- -- ns t able 8. 33c408 ac c haracteristics for r ead c ycle (v cc = 5v + 10%, t a = -55 to +125 c, unless otherwise specified ) p arameter s ymbol m in t yp m ax u nit
memory 6 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 chip select to end of write -20 -25 -30 t cw 14 15 17 -- -- -- -- -- -- ns address setup time -20 -25 -30 t as 0 0 0 -- -- -- -- -- -- ns address valid to end of write -20 -25 -30 t aw 14 15 17 -- -- -- -- -- -- ns write pulse width (oe high) -20 -25 -30 t wp 14 15 17 -- -- -- -- -- -- ns write recovery time -20 -25 -30 t wr 0 0 0 -- -- -- -- -- -- ns write to output in high-z -20 -25 -30 t whz -- -- -- 5 5 6 -- -- -- ns write pulse width (oe low) -20 -25 -30 t wp1 -- -- -- 22 24 26 -- -- -- ns data to write time overlap -20 -25 -30 t dw 9 10 11 -- -- -- -- -- -- ns end write to output low-z -20 -25 -30 t ow -- -- -- 6 7 8 -- -- -- ns data hold from write time -20 -25 -30 t dh 0 0 0 -- -- -- -- -- -- ns t able 10. 33c408 ac c haracteristics for w rite c ycle (v cc = 5v + 10%, t a = -55 to +125 c, unless otherwise specified ) p arameter s ymbol m in t yp m ax u nit
memory 7 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 f igure 1. ac t est l oads f igure 2. t iming w aveform of r ead c ycle (1)
memory 8 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 f igure 3. t iming w aveform of r ead c ycle (2) read cycle notes: 1 .we is high for read cycle. 2 . all read cycle timing is referenc ed form the last valid address to the first transition address. 3 .t hz and t ohz are defined as the time at which the outputs achiev e the open circuit condition and are not referenced to v oh or v ol levels. 4 . at any given temperature and voltage condition, t hz(max) is less than t lz(min) both for a given device and from device to device. 5 . transition is measured + 200mv from steady state voltage wi th load(b). this parameter is sampled and not 100% tested. 6 . device is continuously selected with cs = v il. 7 . address valid prior to coincident with cs transition low. 8 . for common i/o applications, mi nimization or elimination of bus contention c ondition is necessary dur ing read and write cycle. f igure 4. t iming w aveform of w rite c ycle (1)
memory 9 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 f igure 5. t iming w aveform of w rite c ycle (2) f igure 6. t iming w aveform of w rite c ycle (3) w rite c ycle n ote : 1 . all write cycle timing is referenced from the la st valid address to the first transition address. 2 . a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low: a write ends at the earliest transition among cs going high and we going high. t wp is measured from begin- ning of write to the end of write. 3 .t cw is measured from the later of cs going low to end of write. 4 .t as is measured from the address valid to the beginning of write. 5 .t wr is measured form the end of write to the addre ss change. twr applied in case a write ends as cs , or wr going high.
memory 10 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 6 . if oe , cs and we are in the read mode during this period, the i/o pi ns are in the output low-z state. inputs of opposite phase of the output must not be applied because bus contention can occur. 7 . for common i/o applications, minimization or elimination of bus contention conditi ons is necessary during read and write cycle. 8 .ic cs goes low simultaneously with we going low or after we going low, the outputs remain high impedance state. 9 .d out is the read data of the new address. 10 . when cs is low: i/o pins are in the output state. the i nput signals in the opposite phase leading to the output should not be applied.
memory 11 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 f igure 7. sram h eavy i on c ross s ection f igure 8. sram p roton seu c ross s ection s tatic
memory 12 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 f32-06 note: all dimensions in inches 32 p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.120 0.135 0.155 b 0.013 0.015 0.020 c 0.008 0.010 0.012 d -- 0.930 0.940 e 0.635 0.645 0.655 e1 -- -- 0.690 e2 0.550 0.565 -- e3 0.030 0.040 -- e 0.050 bsc l 0.390 0.400 0.410 q 0.026 0.098 -- s1 0.005 0.082 -- n32
memory 13 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 important notice: these data sheets are created using the chip manufacturer s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample test ing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the us e of this information. maxwell technologies? products are not authorized for use as critical components in li fe support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.
memory 14 all data sheets are subject to change without notice ?2001 maxwell technologies all rights reserved. 4 megabit (512k x 8-bit) cmos sram 33c408 12.13.01 rev7 12.20.01 rev 7 1000561 product ordering options model number feature option details 33c408 xx f x -xx access time screening flow package radiation feature base product nomenclature 20 = 20 ns 25 = 25 ns 30 = 30 ns monolithic s = maxwell class s b = maxwell class b e = engineering (testing @ +25c ) i = industrial (testing @ -55c, +25c, +125c) f = flat pack rp = r ad -p ak ? package rt = non-r ad -p ak ? package 4 megabit cmos sram

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